PMware Manticore Discuss a pilot

Manticore by PMware · Commercial pilot in preparation

Your next simulation. Beyond the CPU.

Manticore brings FPGA acceleration to parallel RTL simulation. It maps compatible single-clock Verilog RTL into a statically scheduled program for a manycore array, moving cycle-by-cycle evaluation off general-purpose CPU cores.

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We’re preparing the first commercial pilot. Help shape it around the simulation challenges your team faces.

Manticore logo: an angular lion profile with a scorpion tail MANTICORE / PRODUCT OF PMWARE
  • InputSingle-clock synthesizable Verilog RTL
  • TargetFPGA manycore array. Documented hardware: Alveo U200
  • StatusPublished research origin. PMware commercial pilot in preparation

Where it may help

Built for the simulations that keep you waiting.

Fit depends on your design and your tools. These are the situations worth a conversation.

Compute-heavy synthesizable RTL

Large designs where regression or bring-up time is dominated by evaluating synthesizable logic cycle after cycle, and a CPU-based simulator is the bottleneck.

Architecture exploration

Teams comparing many design variants, parameters or workloads, where every extra hour per run narrows the space you can afford to explore.

Simulation scaling

Workloads where adding CPU threads has stopped paying off. Manticore targets many small parallel cores with a compile-time schedule instead.

Workflow

From RTL to a scheduled array.

A scheduled path from your RTL to a purpose-built FPGA array.

  1. Verilog RTL

    Start with single-clock synthesizable RTL. Language features are assessed during pilot scoping.

  2. RTL preparation

    The design is prepared for execution across a purpose-built array.

  3. Static manycore scheduling

    Work is partitioned across the array, fixing ahead of time what each core computes and when.

  4. FPGA execution

    The compiled program runs on a manycore array implemented on the FPGA.

Architecture

A grid of small cores, scheduled before it runs.

Instead of one fast thread or a few CPU threads synchronizing at run time, the work is spread across many tiles. Computation and communication are placed on a fixed timetable by a static schedule.

Manticore architecture illustration RTL is prepared and passes through a static scheduler into a six by four grid of tiles on an FPGA. A dashed path shows an example schedule across tiles. A bar below the grid represents memory and the host interface. This is an illustration, not measured data. Verilog RTL single-clock, synthesizable RTL preparation elaborate + lower Static scheduler manycore compilation FPGA fabric · illustrative manycore array slot 0 slot 1 slot 2 slot 3 slot 4 global memory · host interface
IllustrationConceptual architecture. Tile count and routing illustrate the approach; they do not represent a measured hardware configuration.

Pilot expectations

A practical, scoped pilot.

Tell us about your design, your current tools, and the result you need. We’ll explore whether a focused Manticore pilot makes sense.

What we would want to learn from you

  • Your RTL workload and how large and long-running it is.
  • The simulator or tools you use today and where they hurt.
  • The outcome that would make a pilot worthwhile.
  • Your FPGA access, for example an Alveo U200 or other cards, or none yet.
  • Constraints: confidentiality, timeline, and support you expect.

How we’ll scope it

  • Upstream research used an Alveo U200 with Vivado 2022.1 and XRT. That is the documented hardware and toolchain.
  • Compatibility with your RTL beyond the published work is assessed per workload, not assumed.
  • Hardware arrangements and commercial support terms are defined together during pilot scoping.
  • Any performance statement for your design would come from a measurement on your design.

Request a demo / discuss a pilot

Research

Built on published research.

Manticore grew from research by Mahyar Emami and collaborators. Explore the published architecture behind the commercial pilot we’re preparing.

Published research
  • A peer-reviewed paper on static bulk-synchronous parallel RTL simulation.
  • Experiments on an Alveo U200 with Vivado 2022.1 and XRT.
Proposed commercial release · PMware
  • A scoped pilot for selected customer workloads, in preparation.
  • Assessment of broader RTL compatibility.
  • Support and onboarding shaped around pilot requirements.

FAQ

Straight answers.

Is Manticore available today?

PMware’s commercial pilot is in preparation. Contact us to discuss your workload and possible evaluation steps.

Do I need an FPGA?

Manticore executes on an FPGA. The documented hardware is the Alveo U200. Tell us what you have or can access. Hardware arrangements, including customer-supplied equipment, are agreed during pilot scoping.

Which RTL does it accept?

The research implementation targets single-clock synthesizable RTL. SystemVerilog support is limited. We’ll assess your design’s language features, clocking, and simulation needs during pilot scoping.

How fast is it?

The published paper reports results for its research workloads. Performance depends on the design and configuration; a useful pilot would measure your workload against your current tools.

Does it replace my current simulator?

It is aimed at specific compute-heavy workloads, not presented as a drop-in replacement for your whole verification flow.

What happens to what I send?

Start with a high-level description by email. We can discuss confidentiality before you share design files or proprietary details.

Contact

Bring a workload. We'll tell you if it fits.

Write to us about a pilot. The button opens your mail app with a short template; if it does not, copy the address and write directly.

support@pmwarelabs.com

Request a demo / discuss a pilot

Helpful to include

  1. Company
  2. RTL simulation workload
  3. Current tools and bottleneck
  4. Desired outcome
  5. FPGA availability
  6. Pilot requirements